1. Field of the Invention
The present invention relates to a failure diagnosis of an LSI of a sequential circuit, and more particularly to estimation of a failure section region of a sequential circuit in an LSI without a failure dictionary.
2. Description of the Related Art
As conventional failure section estimating technique of a sequential circuit of an LSI, various methods are known. For example, in a method, a failure dictionary is previously produced, and the failure dictionary is referred to based on an actually detected failure state to estimate a failure section. Also, there is another method in which the states of flip-flop circuits are read by use of a scan pass to estimate a failure section, as disclosed in Japanese Laid Open Patent Disclosure (JP-A- Heisei 6-194416).
FIG. 1 is a flow chart illustrating an example of the conventional method of estimating a failure section using a failure dictionary. In the conventional example, the simulation when a failure section is inserted in a sequential circuit, i.e., failure simulation is performed using an actual test vector. A failure dictionary data file which indicates a relation of information of the inserted failure section and the failure states of output terminals is previously produced (step S102). After that, a test of a sequential circuit is actually performed using a test vector. The failure dictionary is referred to based on the information of the output terminals of the failure states in the test result to determine a candidate point of the failure section (step S104). This step is performed to all the test vectors. Next, the priority levels are sequentially allocated to the plurality of determined failure candidates from the section having the highest failure possibility for estimating the failure section (step S106).
On the other hand, when a scan pass is used, a checking circuit whose state can be written and read is previously provided in the sequential circuit. The states of flip-flop circuits are set using the checking circuit. After the sequential circuit operates, the states of the flip-flop circuits are read out. The read out states and expected values are compared to determine whether or not the failure state is propagated from a previous stage circuit. The estimation of the failure section is performed based on the determining result.
However, there are problems in the above-mentioned conventional methods of estimating the failure section of the sequential circuit section, as described below.
That is, in the method of using a failure dictionary, it is necessary to previously perform a failure simulation to the whole sequential circuit and to prepare the failure dictionary to the failure outputs. In this case, the failure simulation must be performed, assuming a failure about each of expected nodes such as latch circuits and gate circuits. Therefore, there is a problem in that it takes long time to produce the failure dictionary. In this case, it could be considered that the sequential circuit is grouped into a plurality of parts and that the failure dictionary corresponding to each of the parts is produced. Even in the case, however, a great amount of time would be needed to produce the failure dictionary. The problem would be left that the runtime becomes longer with development of a large scaled sequential circuit.
Also, because a failure model treated in the failure simulation generally is a single degenerated failure, there is the possibility that the estimated failure is not coincident with an actual failure in a multiple failure such as a bridge failure. In such a case, it could be considered that the failure simulation is extended to the multiple failure. However, because the processing time increases to a great extent, the failure simulation is not in practice.
Next, in the method of using a scan pass, it is necessary to incorporate the checking circuit of flip-flop circuits in the sequential circuit. In accordance with, there is a problem that the scan pass method can not be applied in a sequential circuit in which the checking circuit is not incorporated.